﻿@inproceedings{
XIE:SOCC08-HLS,
   Author = {Chen, Yibo and Ouyang, Jin and Xie, Yuan},
   Title = {ILP-based scheme for timing variation-aware scheduling and resource binding},
   BookTitle = {2008 IEEE International SOC Conference},
   Pages = {27-30},
   Year = {2008} }



@inproceedings{
XIE:ASPDAC2009-Latch,
   Author = {Chen, Yibo and Xie, Yuan},
   Title = {Tolerating process variations in high-level synthesis using transparent latches},
   BookTitle = {Asia and South Pacific Design Automation Conference  (ASP-DAC 2009)},
   Pages = {73-78},
   Year = {2009} }



@inproceedings{
xie:aspdac05a,
   Author = {Conner, J. and Xie, Y. and Kandemir, M. and Link, G. and Dick, R.},
   Title = {FD-HGAC: a hybrid heuristic/genetic algorithm hardware/software co-synthesis framework with fault detection},
   BookTitle = {Asia and South Pacific Design Automation Conference},
   Volume = {2},
   Pages = {709-712 Vol. 2},
   Year = {2005} }



@inproceedings{
XIE:ASPDAC09-NBTI,
   Author = {DeBole, M. and Ramakrishnan, K. and Balakrishnan, V. and Wang, Wenping and Luo, Hong and Wang, Yu and Xie, Yuan and Cao, Yu and Vijaykrishnan, N.},
   Title = {A framework for estimating NBTI degradation of microarchitectural components},
   BookTitle = {. Asia and South Pacific Design Automation Conference (ASP-DAC 2009)},
   Pages = {455-460},
   Year = {2009} }



@inproceedings{
xie:isqed04,
   Author = {Degalahal, V. and Ramanarayanan, R. and Vijaykrishnan, N. and Xie, Y. and Irwin, M. J.},
   Title = {The effect of threshold voltages on the soft error rate [memory and logic circuits]},
   BookTitle = {International Symposium on Quality Electronic Devices},
   Pages = {503-508},
   Year = {2004} }



@inproceedings{
xie:socc06-tsinghua,
   Author = {Ding, Qian and Luo, Rong and Wang, Hui and Yang, Huazhong and Xie, Yuan},
   Title = {Modeling the Impact of Process Variation on Critical  Charge Distribution},
   BookTitle = {IEEE International SOC Conference},
   Year = {2006} }



@inproceedings{
xie:asicon05-ser,
   Author = {Ding, Qian and LUO, Rong and XIE, Yuan},
   Title = {Impact of Process Variation on Soft Error Vulnerability for Nanometer VLSI Circuits},
   BookTitle = {International Conference on ASICs},
   Year = {2005} }



@inproceedings{
Xie:dac08,
   Author = {Dong, Xiangyu and Wu, Xiaoxia and Sun, Guangyu and Xie, Y. and Li, H. and Chen, Yiran},
   Title = {Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement},
   BookTitle = {Design Automation Conference, 2008. DAC 2008. 45th ACM/IEEE},
   Pages = {554-559},
   Year = {2008} }



@inproceedings{
XIE:ASPDAC2009-3Dcost,
   Author = {Dong, Xiangyu and Xie, Yuan},
   Title = {System-level cost analysis and design exploration for three-dimensional integrated circuits (3D ICs)},
   BookTitle = { Asia and South Pacific Design Automation Conference (ASP-DAC 2009)},
   Pages = {234-241},
   Year = {2009} }



@inproceedings{
Xie:Nanoarch09,
   Author = {Eachempati, S. and Xie, Yuan and Narayanan, V. and Yanamandra, A. and Irwin, M. J.},
   Title = {Power and area reduction using carbon nanotube bundle interconnect in global clock tree distribution network},
   BookTitle = {IEEE/ACM International Symposium on Nanoscale Architectures },
   Pages = {51-56},
   Year = {2009} }



@inproceedings{
xie:iccad07,
   Author = {Feng, Wang and Nicopoulos, C. and Xiaoxia, Wu and Yuan, Xie and Vijaykrishnan, N.},
   Title = {Variation-aware task allocation and scheduling for MPSoC},
   BookTitle = {Computer-Aided Design, 2007. ICCAD 2007. IEEE/ACM International Conference on},
   Pages = {598-603},
   Year = {2007} }



@inproceedings{
   xie:aspdac08-bp,
   Author = {Feng, Wang and Xiaoxia, Wu and Yuan, Xie},
   Title = {Variability-driven module selection with joint design time optimization and post-silicon tuning},
   BookTitle = {Design Automation Conference, 2008. ASPDAC 2008. Asia and South Pacific},
   Pages = {2-9},
   Year = {2008} }



@inproceedings{
   Author = {Hai, Lin and Guangyu, Sun and Yunsi, Fei and Yuan, Xie and Sivasubramaniam, A.},
   Title = {Thermal-aware Design Considerations for Application-Specific Instruction Set Processor},
   BookTitle = {Application Specific Processors, 2008. SASP 2008. Symposium on},
   Pages = {63-68},
   Year = {2008} }



@inproceedings{
xie:isvlsi05,
   Author = {Hostetler, D. and Xie, Yuan},
   Title = {Adaptive power management in software radios using resolution adaptive analog to digital converters},
   BookTitle = { IEEE Computer Society Annual Symposium on  Emerging VLSI Technologies and Architectures },
   Pages = {186-191},
   Year = {2005} }



@inproceedings{
xie:iccd04,
   Author = {Hung, W. and Addo-Quaye, C. and Theocharides, T. and Xie, Y. and Vijakrishnan, N. and Irwin, M. J.},
   Title = {Thermal-aware IP virtualization and placement for networks-on-chip architecture},
   BookTitle = {IEEE International Conference on Computer Design.},
   Pages = {430-437},
   Year = {2004} }



@inproceedings{
xie:islped04,
   Author = {Hung, W. and Xie, Y. and Vijaykrishnan, N. and Kandemir, M. and Irwin, M. J. and Tsai, Y.},
   Title = {Total Power Optimization through Simultaneously Multiple-VDD Multiple-VTH Assignment and Device Sizing with Stack Forcing},
   BookTitle = {International Symposium on Low Power Electronics and Design.},
   Pages = {144-149},
   Year = {2004} }



@inproceedings{
xie:iccd05-vi,
   Author = {Hung, W. L. and Link, G. M. and Xie, Yuan and Vijaykrishnan, N. and Dhanwadaf, N. and Conner, J.},
   Title = {Temperature-aware voltage islands architecting in system-on-chip design},
   BookTitle = {International Conference on Computer Design},
   Pages = {689-694},
   Year = {2005} }



@inproceedings{
xie:isqed06-3d,
   Author = {Hung, W. L. and Link, G. M. and Xie, Y. and Vijaykrishnan, N. and Irwin, M. J.},
   Title = {Interconnect and Thermal-aware Floorplanning for 3D Microprocessors},
   BookTitle = {International Symposium on Quality Electronic Device},
   Pages = {98-104},
   Year = {2006} }



@inproceedings{
xie:isqed05-thermal,
   Author = {Hung, W. L. and Xie, Y. and Vijaykrishnan, N. and Addo-Quaye, C. and Theocharides, T. and Irwin, M. J.},
   Title = {Thermal-aware floorplanning using genetic algorithms},
   BookTitle = {Sixth International Symposium on  Quality of Electronic Design },
   Pages = {634-639},
   Year = {2005} }



@inproceedings{
xie:date05-thermal,
   Author = {Hung, W. L. and Xie, Y. and Vijaykrishnan, N. and Kandemir, M. and Irwin, M. J.},
   Title = {Thermal-aware task allocation and scheduling for embedded systems},
   BookTitle = {Design Automation and Test in Europe.},
   Pages = {898-899 Vol. 2},
   Year = {2005} }



@inproceedings{
xie:iccad06,
   Author = {Hung, Wei-lun and Wu, Xiaoxia and Xie, Yuan},
   Title = {Guarantee Performance Yield in High Level Synthesis},
   BookTitle = {International Conference on Computer Aids Design},
   Year = {2006} }



@inproceedings{
xie:isqed07-ser,
   Author = {Krishnan, Ramakrishnan and Ramanarayanan, Rajaraman and Srinivasan, Suresh and Narayanan, Vijaykrishnan and Xie, Yuan and Irwin, Mary Jane},
   Title = {Variation Impact on SER of Combinational Circuits.  },
   BookTitle = {International Symopsium on on Quality Electronic Devices (ISQED)},
   Year = {2007} }



@inproceedings{
xie:isca06,
   Author = {Li, F. and Nicopoulos, C. and Richardson, T. and Xie, Y. and Vijaykrishnan, N. and Kandemir, M.},
   Title = {Design and management of 3D chip multiprocessors using network-in-memory},
   BookTitle = {International Symposium on Computer Architecture (ISCA'06)},
   Year = {2006} }



@inproceedings{
xie:date04,
   Author = {Lin, Chang Hong and Xie, Yuan and Wolf, W.},
   Title = {LZW-based code compression for VLIW embedded systems},
   BookTitle = {Design Automation and Test in Europe},
   Volume = {3},
   Pages = {76-81  },
   Year = {2004} }



@inproceedings{
xie:isqed07-nbti,
   Author = {Luo, Hong and Wang, Yu and He, Ku and Luo, Rong and Yang, Huazhong and Xie, Yuan},
   Title = {Modeling of PMOS NBTI Effect Considering Temperature Variation},
   BookTitle = { International Symposium on Quality Electronic Devices (ISQED)},
   Year = {2007} }



@article{
Xie:IEICE09,
   Author = {Luo, Hong and Wang, Yu and Luo, Rong and Yang, Huazhong and Xie, Yuan},
   Title = {Temperature-aware NBTI Modeling Techniques in Digital Circuits},
   Journal = {IEICE Transactions on Electronics},
   Volume = {6},
   Pages = {875-886},
   Year = {2009} }



@article{
Xie:IJPP09,
   Author = {M. DeBole and R. Krishnan and V. Balakrishnan and W. Wang and H. Luo and Y. Wang and Y. Xie and Y. Cao and Vijaykrishnan, N.},
   Title = {New-Age: A Negative Bias Temperature Instability-Estimation Framework for Microarchitectural Components.},
   Journal = {International Journal of Parallel Programming},
   Volume = {37},
   Number = {4},
   Pages = {417-431},
   Year = {2009} }



@inproceedings{
xie:glsvisl08-pram,
   Author = {Mangalagiri, Prasanth and Sarpatwari, Karthik and Yanamandra, Aditya and Narayanan, VijayKrishnan and Xie, Yuan and Irwin, Mary Jane and Karim, Osama Awadel},
   Title = {A low-power phase change memory based hybrid cache architecture},
   BookTitle = {Proceedings of the 18th ACM Great Lakes symposium on VLSI},
   Address= {Orlando, Florida, USA},
   Publisher = {ACM},
   Pages = {395-398},
   Year = {2008} }



@inproceedings{
   Author = {Mangalagiri, P. and Sungmin, Bae and Krishnan, R. and Yuan, Xie and Narayanan, V.},
   Title = {Thermal-aware reliability analysis for Platform FPGAs},
   BookTitle = {Computer-Aided Design, 2008. ICCAD 2008. IEEE/ACM International Conference on},
   Pages = {722-727},
   Year = {2008} }



@inproceedings{
xie:tutorial-isca05,
   Author = {Mitra, S. and Vijaykrishnan, N. and Spainhower, L. and Xie, Y.},
   Title = {Tutorial: Robust System Design from Unreliable Components},
   BookTitle = {The 32nd Annual International Symposium on Computer Architecture (ISCA)},
   Year = {2005} }



@inproceedings{
xie:isvlsi06-bus,
   Author = {Mutyam, M. and Eze, M. and Vijaykrishnan, N. and Xie, Y.},
   Title = {Delay and energy efficient data transmission for on-chip buses},
   BookTitle = {IEEE Computer Society Annual Symposium on  Emerging VLSI Technologies and Architectures },
   Volume = {00},
   Pages = {6 pp.},
   Year = {2006} }



@article{
Xie:TC09,
   Author = {Mutyam, M. and Wang, Feng and Krishnan, R. and Narayanan, V. and Kandemir, M. and Xie, Yuan and Irwin, M. J.},
   Title = {Process-Variation-Aware Adaptive Cache Architecture and Management},
   Journal = { IEEE Transactions on Computers},
   Volume = {58},
   Number = {7},
   Pages = {865-877},
   Year = {2009} }



@inproceedings{
xie:iccd05-loop,
   Author = {Narayanan, S. H. K. and Chen, G. and Kandemir, M. and Xie, Y.},
   Title = {Temperature-sensitive loop parallelization for chip multiprocessors},
   BookTitle = {International Conference on Computer Design},
   Pages = {677-682},
   Year = {2005} }



@article{
xie:computer06,
   Author = {Narayanan, V and Xie, Yuan},
   Title = {Reliability concerns in embedded system designs},
   Journal = {IEEE Computer},
   Volume = {39},
   Number = {1},
   Pages = {118-120},
   Year = {2006} }



@inproceedings{
Xie:3DIC09-adder,
   Author = {Ouyang, J. and Sun, G. and Chen, Y. and Duan, L. and Zhang, T. and Xie, Y. and Irwin, M. J.},
   Title = {Arithmetic unit design using 180nm TSV-based 3D stacking technology},
   BookTitle = { IEEE International Conference on 3D System Integration},
   Pages = {1-4},
   Year = {2009} }



@inproceedings{
xie:aspdac06,
   Author = {Ozturk, O. and Wang, Feng and Kandemir, M. and Xie, Yuan},
   Title = {Optimal topology exploration for application-specific 3D architectures},
   BookTitle = {Asia and South Pacific Design Automation Conference},
   Pages = {6 pp.},
   Year = {2006} }

@inproceedings{
xie:pcramsim,
   Author = {Xiangyu Dong and Norm Jouppi and Yuan Xie  },
   Title = {PCRAMsim: System-Level Performance, Energy, and Area Modeling for
Phase-Change RAM},
   BookTitle = {Proceedings of International Conference on Computer-Aided Design (ICCAD)},
   Pages = {269-275},
   Year = {2009} }      


@inproceedings{
xie:isca08,
   Author = {Park, Dongkook and Eachempati, S. and Das, R. and Mishra, A. K. and Xie, Y. and Vijaykrishnan, N. and Das, C. R.},
   Title = {MIRA: A Multi-layered On-Chip Interconnect Router Architecture},
   BookTitle = {Computer Architecture, 2008. ISCA '08. 35th International Symposium on},
   Pages = {251-261},
   Year = {2008} }
 @article{
Xie:TDSC09-SER,
   Author = {Ramanarayanan, R. and Degalahal, V. S. and Krishnan, R. and Kim, Jungsub and Narayanan, V. and Xie, Yuan and Irwin, M. J. and Unlu, K.},
   Title = {Modeling Soft Errors at the Device and Logic Levels for Combinational Circuits},
   Journal = { IEEE Transactions on Dependable and Secure Computing},
   Volume = {6},
   Number = {3},
   Pages = {202-216},
   Year = {2009} }



@inproceedings{
xie:vlsid06-raj,
   Author = {Ramanarayanan, R. and Kim, J. S. and Vijaykrishnan, N. and Xie, Y. and Irwin, M. J.},
   Title = {SEAT-LA: A Soft Error Analysis tool for Combinational Logic. },
   BookTitle = {IEEE International Conference on VLSI Design},
   Year = {2006} }



@inproceedings{
xie:selse06-raj,
   Author = {Ramanarayanan, R. and Krishnan, R. and Vijaykrishnan, N. and Xie, Yuan and Irwin, Mary J.},
   Title = {Temperature and Voltage Scaling Effects on Electrical Masking,},
   BookTitle = {The Second Workshop on System Effects of Logic Soft Errors},
   Year = {2006} }



@inproceedings{
xie:vlsid06-bus,
   Author = {Richardson, T. D. and Nicopoulos, C. and Park, D. and Narayanan, V. and Xie, Yuan and Das, C. and Degalahal, V.},
   Title = {A hybrid SoC interconnect with dynamic TDMA-based transaction-less buses and on-chip networks},
   BookTitle = {International Conference on VLSI Design},
   Pages = {8 pp.},
   Year = {2006} }



@inproceedings{
xie:asic05,
   Author = {Richardson, T. D. and Xie, Yuan},
   Title = {Evaluation of Thermal-Aware Design Techniques for Microprocessors},
   BookTitle = {International Conference on ASICs},
   Volume = {1},
   Pages = {62-65},
   Year = {2005} }



@inproceedings{
XIE:ASPDAC09-3D,
   Author = {Sridharan, S. and DeBole, M. and Sun, Guangyu and Xie, Yuan and Narayanan, V.},
   Title = {A criticality-driven microarchitectural three dimensional (3D) floorplanner},
   BookTitle = {Asia and South Pacific Design Automation Conference　 },
   Pages = {763-768},
   Year = {2009} }



@inproceedings{
xie:iccad04,
   Author = {Srinivasan, S. and Gayasen, A. and Vijaykrishnan, N. and Kandemir, M. and Xie, Y. and Irwin, M. J.},
   Title = {Improving soft-error tolerance of FPGA configuration bits},
   BookTitle = { IEEE/ACM International Conference on  Computer Aided Design },
   Pages = {107-110},
   Year = {2004} }



@article{
XIE:TDSC2008-FPGA,
   Author = {Srinivasan, S. and Krishnan, R. and Mangalagiri, P. and Xie, Yuan and Narayanan, V. and Irwin, M. J. and Sarpatwari, K.},
   Title = {Toward Increasing FPGA Lifetime},
   Journal = { IEEE Transactions on Dependable and Secure Computing},
   Volume = {5},
   Number = {2},
   Pages = {115-127},
   Year = {2008} }



@inproceedings{
xie:dac06,
   Author = {Srinivasan, Suresh and Mangalagiri, Prashanth and Sarpatwari, Karthik and Xie, Yuan and Vijaykrishnan, N.},
   Title = {FLAW: FPGA Lifetime AWareness},
   BookTitle = {Design Automation Conference (DAC)},
   Year = {2006} }



@inproceedings{
XIE:HPCA09,
   Author = {Sun, Guangyu and Dong, Xiangyu and Xie, Yuan and Li, Jian and Chen, Yiran},
   Title = {A novel architecture of the 3D stacked MRAM L2 cache for CMPs},
   BookTitle = { IEEE 15th International Symposium on High Performance Computer Architecture, 2009.  },
   Pages = {239-249},
   Year = {2009} }



@misc{
xie:glsvlsi08-tutorial,
   Author = {Syed, M. Alam and Mike, Ignatowski and Yuan, Xie},
   Title = {Tutorial:  Technology, CAD tools, and designs for emerging 3D integration technology},
   Publisher = {ACM},
   Note = {1366112
1-2},
         Year = {2008} }



@article{
3D:BEE3,
   Author = {Thacker, Chuck and Davis, John},
   Title = {BEE3: Revitalizing Computer Architecture Research},
   Journal = {Microsoft Research Technical Report, http://research.microsoft.com/projects/BEE3},
   Year = {2008} }



@inproceedings{
xie:date05-tosun,
   Author = {Tosun, S. and Mansouri, N. and Arvas, E. and Kandemir, M. and Xie, Y.},
   Title = {Reliability-centric high-level synthesis},
   BookTitle = {Design Automation and Test in Europe},
   Pages = {1258-1263 Vol. 2},
   Year = {2005} }



@inproceedings{
xie:isqed05-tosun,
   Author = {Tosun, S. and Mansouri, N. and Arvas, E. and Kandemir, M. and Xie, Y. and Hung, W. L.},
   Title = {Reliability-centric hardware/software co-design},
   BookTitle = {Sixth International Symposium on  Quality of Electronic Design},
   Pages = {375-380},
   Year = {2005} }



@inproceedings{
xie:isqed05-hls,
   Author = {Tosun, S. and Ozturk, O. and Mansouri, N. and Arvas, E. and Kandemir, M. and Xie, Y. and Hung, W. L.},
   Title = {An ILP formulation for reliability-oriented high-level synthesis},
   BookTitle = {Sixth International Symposium on  Quality of Electronic Design },
   Pages = {364-369},
   Year = {2005} }



@inproceedings{
xie:date05-noc,
   Author = {Tsai, Yuh-Fang and Narayaynan, V. and Xie, Yuan and Irwin, M. J.},
   Title = {Leakage-aware interconnect for on-chip network},
   BookTitle = {Design Automation and Test in Europe},
   Pages = {230-231 Vol. 1},
   Year = {2005} }



@inproceedings{
xie:vlsid05-variation,
   Author = {Tsai, Yuh-Fang and Vijaykrishnan, N. and Xie, Yuan and Irwin, M. J.},
   Title = {Influence of leakage reduction techniques on delay/leakage uncertainty},
   BookTitle = {International Conference on VLSI Design},
   Pages = {374-379},
   Year = {2005} }



@article{
XIE:TVLSI2008-3DCacti,
   Author = {Tsai, Yuh-Fang and Wang, Feng and Xie, Yuan and Vijaykrishnan, N. and Irwin, M. J.},
   Title = {Design Space Exploration for 3-D Cache},
   Journal = { IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
   Volume = {16},
   Number = {4},
   Pages = {444-455},
   Year = {2008} }



@inproceedings{
xie:iccd05-3d,
   Author = {Tsai, Yuh-Fang and Xie, Yuan and Vijaykrishnan, N. and Irwin, M. J.},
   Title = {Three-dimensional cache design exploration using 3DCacti},
   BookTitle = {International Conference on Computer Design (ICCD)},
   Pages = {519-524},
   Year = {2005} }



@inproceedings{
Xie:ICCAD09-PV,
   Author = {Vaidyanathan, Balaji and Oates, Anthony S. and Xie, Yuan},
   Title = {Intrinsic NBTI-Variability Aware Statistical Pipeline Performance Assessment and Tuning},
   BookTitle = {International Conference on Computer-Aided Design (ICCAD)},
   Pages = {164-171},
   Year = {2009} }



@inproceedings{
XIE:ISQED2009,
   Author = {Vaidyanathan, Balaji and Oates, Anthony S. and Yuan, Xie and Yu, Wang},
   Title = {NBTI-aware statistical circuit delay assessment},
   BookTitle = {Quality of Electronic Design, 2009. ISQED 2009. Quality of Electronic Design},
   Pages = {13-18},
   Year = {2009} }



@inproceedings{
Xie:MTDT09,
   Author = {Vaidyanathan, B. and Wang, Yu and Xie, Yuan},
   Title = {Cost-Aware Lifetime Yield Analysis of Heterogeneous 3D On-chip Cache},
   BookTitle = {  IEEE International Workshop on Memory Technology, Design, and Testing},
   Pages = {65-70},
   Year = {2009} }



@inproceedings{
xie:socc06-balaji,
   Author = {Vaidyanathan, Balaji and Xie, Yuan},
   Title = {Crosstalk-Aware Energy Efficient Encoding for Instruction Bus through Code Compression},
   BookTitle = {IEEE International SOC Conference},
   Year = {2006} }



@inproceedings{
xie:apccas06,
   Author = {Vaidyanathan, Balaji and Xie, Yuan and Vijaykrishnan, N.},
   Title = {Leakage Optimized DECAP Design for FPGAs},
   BookTitle = {IEEE ASia Pacific Conference on Circuits and Systems},
   Year = {2006} }



@inproceedings{
xie:selse06-balaji,
   Author = {Vaidyanathan, Balaji and Xie, Yuan and Vijaykrishnan, N. and Zheng, Hao},
   Title = {Soft Error Analysis and Optimizations of C-elements in Asynchronous Circuits},
   BookTitle = {The Second Workshop on System Effects of Logic Soft Errors},
   Year = {2006} }



@inproceedings{
xie:date08,
   Author = {Wang, Feng and Sun, Guangyu and Xie, Yuan},
   Title = {A Variation Aware High Level Synthesis Framework},
   BookTitle = {Design, Automation and Test in Europe, 2008. DATE '08},
   Pages = {1063-1068},
   Year = {2008} }



@inproceedings{
xie:aspdac08,
   Author = {Wang, Feng and Wu, Xiaoxia and Xie, Y.},
   Title = {Variability-driven module selection with joint design time optimization and post-silicon tuning},
   BookTitle = {Design Automation Conference, 2008. ASPDAC 2008. Asia and South Pacific},
   Pages = {2-9},
   Year = {2008} }



@inproceedings{
xie:selse06-wang,
   Author = {Wang, Feng and Xie, Yuan},
   Title = {An Accurate and Efficient Model of Electrical Masking Effect for SE in Combinatorial Logic},
   BookTitle = {The Second Workshop on System Effects of Logic Soft Errors},
   Year = {2006} }



@techreport{
xie:criticality,
   Author = {Wang, Feng and Xie, Yuan},
   Title = {A Fast and Accurate Criticality Computation Method in Statistical Timing Analysis},
   Institution = {Pennsylvania State University},
   Number = {Technical Report, Computer Science Engineering Department},
   Month= {May},
      Year = {2006} }



@inproceedings{
xie:date07-timing,
   Author = {Wang, Feng and Xie, Yuan},
   Title = {A Novel Criticality Computation Method in Statistical Timing Analysis},
   BookTitle = {Design Automation and Test in Europe},
   Year = {2007} }



@inproceedings{
xie:dac07-module,
   Author = {Wang, Feng and Xie, Yuan},
   Title = {Variation-aware Module Selection Algorithm for Synthesis},
   BookTitle = {submitted to Design Automation Conference},
   Year = {2007} }



@inproceedings{
xie:IPDPS08,
   Author = {Wang, Feng and Xie, Y.},
   Title = {Embedded Multi-Processor System-on-chip (MPSoC) design considering process variations},
   BookTitle = {Parallel and Distributed Processing, 2008. IPDPS 2008. IEEE International Symposium on},
   Pages = {1-5},
   Year = {2008} }



@inproceedings{
xie:isvlsi06-finfet,
   Author = {Wang, Feng and Xie, Yuan and Bernstein, K. and Luo, Yan},
   Title = {Dependability analysis of nano-scale FinFET circuits},
   BookTitle = { IEEE Computer Society Annual Symposium on  Emerging VLSI Technologies and Architectures },
   Volume = {00},
   Pages = {6 pp.},
   Year = {2006} }



@inproceedings{
xie:vlsid07-ser,
   Author = {Wang, Feng and Xie, Yuan and Ramanarayanan, R.},
   Title = {Soft Error Rate Analysis for Combinational Logic Using An Accurate Electrical Masking Model},
   BookTitle = {International Conference on VLSI Design},
   Year = {2007} }



@inproceedings{
XIE:ASPDAC2009-Mentor,
   Author = {Wang, Feng and Xie, Yuan and Takach, A.},
   Title = {Variation-aware resource sharing and binding in behavioral synthesis},
   BookTitle = {Asia and South Pacific Design Automation Conference (ASPDAC 2009)},
   Pages = {79-84},
   Year = {2009} }



@inproceedings{
Xie:DATE09-Wangyu,
   Author = {Wang, Yu and Chen, Xiaoming and Wang, Wenping and Cao, Yu and Xie, Yuan and Yang, Huazhong},
   Title = {Gate replacement techniques for simultaneous leakage and aging optimization},
   BookTitle = {Design, Automation and Test in Europe Conference },
   Pages = {328-333},
   Year = {2009} }



@inproceedings{
xie:date07-nbti,
   Author = {Wang, Yu and Luo, Hong and He, Ku and Luo, Rong and Xie, Yuan and Yang, Huazhong},
   Title = {Temperature-aware NBTI modeling and the impact of input vector control on performance degradation},
   BookTitle = {Design Automation and Test in Europe},
   Year = {2007} }



@inproceedings{
xie:iccd08-3d,
   Author = {Wu, Xiaoxia and Chen, Yibo and Xie, Y. and Chakrabarty, Krish},
   Title = {Test-Access Mechanism Optimization for Core-Based Three-Dimensional SOCs},
   BookTitle = {International Conference on Computer Design},
   Year = {2008} }



@inproceedings{
xie:iccd07-3d,
   Author = {Wu, Xiaoxia and Frankstein, Paul and Xie, Y.},
   Title = {Scan Chain Design for Three-dimentional(3D) ICs},
   BookTitle = {International Conference on Computer Design},
   Year = {2007} }



@inproceedings{
Xie:ISCA09,
   Author = {Wu, Xiaoxia and Li, Jian and Zhang, Lixin and Speight, Evan and Rajamony, Ram and Xie, Yuan},
   Title = {Hybrid Cache Architecture with Disparate Memory Technologies},
   BookTitle = {International Conference on Computer Architecture (ISCA)},
   Pages = {34-45},
   Year = {2009} }



@inproceedings{
XIE:SiPS2008,
   Author = {Wu, Xuebin and Yan, Zhiyuan and Xie, Yuan},
   Title = {Two-dimensional crosstalk avoidance codes},
   BookTitle = { IEEE Workshop on Signal Processing Systems (SiPS 2008)},
   Pages = {106-111},
   Year = {2008} }



 


@inproceedings{
   XIE:ICCD08-3D,
   Author = {Xiaoxia, Wu and Yibo, Chen and Chakrabarty, K. and Yuan, Xie},
   Title = {Test-access mechanism optimization for core-based three-dimensional SOCs},
   BookTitle = {Computer Design, 2008. ICCD 2008. IEEE International Conference on},
   Pages = {212-218},
   Year = {2008} }



@inproceedings{
   Author = {Xiaoxia, Wu and Yibo, Chen and Chakrabarty, K. and Yuan, Xie},
   Title = {Test-Access Solutions for Three-Dimensional SOCs},
   BookTitle = {Test Conference, 2008. ITC 2008. IEEE International},
   Pages = {1-1},
   Year = {2008} }



@phdthesis{
xie:thesis,
   Author = {Xie, Yuan},
   Title = {Code Compression and Decompression Architectures for Embedded VLIW Processors},
   School = {Princeton University},
      Year = {2002} }



@inproceedings{
xie:tutorial-aspdac05,
   Author = {Xie, Y.},
   Title = {Tutorial:  Designing Reliable Circuits},
   BookTitle = {Asia and South Pacific Design Automation Conference},
   Year = {2005} }



@inproceedings{
xie:tutorial-asic05,
   Author = {Xie, Y.},
   Title = {Tutorial:  Thermal-Aware Design Techniques for Nanometer VLSI Design},
   BookTitle = {International Conference on ASICs},
   Year = {2005} }



@article{
Xie:HLS-DandT09,
   Author = {Xie, Yuan and Chen, Yibo},
   Title = {Statistical High-Level Synthesis under Process Variability},
   Journal = {IEEE Design and Test of Computers},
   Volume = {26},
   Number = {4},
   Pages = {78-87},
   Year = {2009} }



@article{
xie:jvlsi06-mpsoc,
   Author = {Xie, Y. and Hung, W.},
   Title = {Temperature-Aware Task Allocation and Scheduling for Embedded Multiprocessor Systems-on-chip (MPSoC) Design},
   Journal = {Journal of VLSI for Signal Processing, to appear.},
   Year = {2006} }



@inproceedings{
xie:asap04,
   Author = {Xie, Y. and Li, L. and Kandemir, M. and Vijaykrishnan, N. and Irwin, M. J.},
   Title = {Reliability-aware co-synthesis for embedded systems},
   BookTitle = {15th IEEE International Conference on  Application-Specific Systems, Architectures and Processors },
   Pages = {41-50},
   Year = {2004} }



@article{
xie:jvlsi06,
   Author = {Xie, Y. and Li, L. and Kandemir, M. and Vijaykrishnan, N. and Irwin, M. J.},
   Title = {Reliability-aware co-synthesis for embedded systems},
   Journal = {Journal of VLSI for Signal Processing},
   Pages = {to appear.},
   Year = {2006} }



@inproceedings{
xie:sasimi00,
   Author = {Xie, Y. and Lin, H. and Wu, Z. and Wolf, W. and Kyoto, Japan.},
   Title = {CAD Techniques for Multimedia System Design},
   BookTitle = {The Ninth Workshop on Synthesis and System Integration of MIxed Technologies  },
   Year = {2000} }



@article{
xie:jetcs06,
   Author = {Xie, Y. and Loh, G and Black, B and Bernstein, K.},
   Title = {Design Space Exploration for 3D Architectures},
   Journal = {ACM Journal of Emerging Technologies in Compuing Systems},
   Year = {2006} }



@inproceedings{
xie:tutorial-micro06,
   Author = {Xie, Y. and Loh, G. and Black, B. and Bernstein, K.},
   Title = {Tutorial: 3D Integration  for Microarchitecture},
   BookTitle = {The 39th Annual IEEE/ACM International Symposium on Microarchitecture},
   Year = {2006} }



@inproceedings{
XIE:ICSICT08,
   Author = {Xie, Yuan and Ma, Yuchun},
   Title = {Design space exploration for 3D integrated circuits},
   BookTitle = {Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on},
   Pages = {2317-2320},
   Year = {2008} }



@inproceedings{
xie:tutorial-asplos04,
   Author = {Xie, Y. and Vijaykrishnan, N.},
   Title = {Tutorial:  Computing in the Presence of Soft Errors},
   BookTitle = {11th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)},
   Year = {2004} }



@inproceedings{
xie:aspdac00,
   Author = {Xie, Yuan and Wolf, W.},
   Title = {Co-synthesis with custom ASICs},
   BookTitle = {Asia and South Pacific Design Automation Conference},
   Pages = {129-133},
   Year = {2000} }



@inproceedings{
xie:date01,
   Author = {Xie, Yuan and Wolf, W.},
   Title = {Allocation and scheduling of conditional task graph in hardware/software co-synthesis},
   BookTitle = {Design Autmation and Test in Europe },
   Pages = {620-625},
   Year = {2001} }



@inproceedings{
xie:asic01a,
   Author = {Xie, Yuan and Wolf, W.},
   Title = {ASICosyn: co-synthesis of conditional task graphs with custom ASICs},
   BookTitle = {International Conference on ASICs},
   Pages = {130-135},
   Year = {2001} }



@inproceedings{
xie:micro01,
   Author = {Xie, Yuan and Wolf, W. and Lekatsas, H.},
   Title = {A code decompression architecture for VLIW processors},
   BookTitle = {34th ACM/IEEE International Symposium on Microarchitecture},
   Pages = {66-75},
   Year = {2001} }



@inproceedings{
xie:asic01b,
   Author = {Xie, Yuan and Wolf, W. and Lekatsas, H.},
   Title = {Compression ratio and decompression overhead tradeoffs in code compression for VLIW architectures},
   BookTitle = {International Conference on ASICs},
   Pages = {337-340},
   Year = {2001} }



@inproceedings{
xie:isss02,
   Author = {Xie, Yuan and Wolf, W. and Lekatsas, H.},
   Title = {Code compression for VLIW processors using variable-to-fixed coding},
   BookTitle = {International Symposium on System Synthesis},
   Pages = {138-143},
   Year = {2002} }



@inproceedings{
xie:dcc03,
   Author = {Xie, Yuan and Wolf, W. and Lekatsas, H.},
   Title = {Code compression using variable-to-fixed coding based on arithmetic coding},
   BookTitle = {Data Compression Conference},
   Pages = {382-391},
   Year = {2003} }



@inproceedings{
xie:date03,
   Author = {Xie, Yuan and Wolf, W. and Lekatsas, H.},
   Title = {Profile-driven selective code compression [embedded systems]},
   BookTitle = {Design Automation and Test in Europe},
   Pages = {462-467},
   Year = {2003} }



@article{
xie:tvlsi06,
   Author = {Xie, Y. and Wolf, W. and Lekatsas, H.},
   Title = {Code Compression for Embedded VLIW Processors Using Variable-to-Fixed Coding},
   Journal = {Very Large Scale Integration (VLSI) Systems, IEEE Transactions on},
   Volume = {14},
   Number = {5},
   Pages = {525-536},
   Year = {2006} }



@article{
xie:jcsc03,
   Author = {Xie, Y. and Xu, J. and Wolf, W.},
   Title = {Augmenting Platform-based Design with Synthesis Tools},
   Journal = {Journal of Circuits, Systems and Computers},
   Volume = {12},
   Number = {2},
   Pages = {125-142},
   Year = {2003} }



@inproceedings{
xie:glsvlsi04,
   Author = {Xu, Wei and Vijaykrishnan, N. and Xie, Y. and Irwin, M. J.},
   Title = {Design of a nanosensor array architecture },
   BookTitle = {the 14th ACM Great Lakes symposium on VLSI },
   Pages = {298-303},
   Year = {2004} }



@article{
XIE:TVLSI08-Yang,
   Author = {Yang, Shengqi and Wang, Wenping and Lu, Tiehan and Wolf, W. and Vijaykrishnan, N. and Xie, Yuan},
   Title = {Case Study of Reliability-Aware and Low-Power Design},
   Journal = {Very Large Scale Integration (VLSI) Systems, IEEE Transactions on},
   Volume = {16},
   Number = {7},
   Pages = {861-873},
   Year = {2008} }



@inproceedings{
xie:date05b,
   Author = {Yang, Shengqi and Wolf, W. and Vijaykrishnan, N. and Serpanos, D. N. and Xie, Yuan},
   Title = {Power attack resistant cryptosystem design: a dynamic voltage and frequency switching approach},
   BookTitle = {Design, Automation and Test in Europe},
   Pages = {64-69  },
   Year = {2005} }



@inproceedings{
xie:isvlsi06-soc,
   Author = {Yang, Shengqi and Wolf, W. and Vijaykrishnan, N. and Xie, Y.},
   Title = {Reliability-aware SOC voltage islands partition and floorplan},
   BookTitle = {IEEE Computer Society Annual Symposium on  Emerging VLSI Technologies and Architectures },
   Volume = {00},
   Year = {2006} }



@inproceedings{
xie:vlsid05a,
   Author = {Yang, Shengqi and Wolf, W. and Vijaykrishnan, N. and Xie, Yuan and Wang, Wenping},
   Title = {Accurate stacking effect macro-modeling of leakage power in sub-100 nm circuits},
   BookTitle = { 18th International Conference on  VLSI Design },
   Pages = {165-170},
   Year = {2005} }



@inproceedings{
xie:aspdac05b,
   Author = {Yang, Shengqi and Wolf, W. and Wang, Wenping and Vijaykrishnan, N. and Xie, Yuan},
   Title = {Low-leakage robust SRAM cell design for sub-100nm technologies},
   BookTitle = {Asia and South Pacific  Design Automation Conference },
   Volume = {1},
   Pages = {539-544 Vol. 1},
   Year = {2005} }



